University of California at Berkeley
College of Engineering
Department of Electrical Engineering and Computer Science
CS61C, Fall 2004
Homework 6: Verilog Adder
TA In Charge
Paul
Submission
Create a folder called 'hw6', place your solutions in this folder, and run 'submit hw6'. Due Wednesday November 3, at 11.59pm
Goals
In this homework you
will gain experience designing and simulating a combinational logic
circuit, a
4-bit adder/subtractor. It will give you
practice
using Verilog for logic simulation and an appreciation for the issues
involved
in designing, testing, and debugging combinational logic circuits.
Reading
Sections
1–5 of “CS61c: Verilog Tutorial”.
Background
Binary
adders are explained in detail in P&H and in
Wawrzynek’s
lecture notes on “Combinational Logic Blocks”. Both sources show how
multi-bit
adders are built from 1-bit adders; in this homework, you will
implement a 4-bit
adder/subtracter out of 1-bit adders.
A truth table for a 1-bit
adder provides
a prescription for the operation and guides the rest of the design.
Assume that
the single bits to be added are represented as a
and b. We denote
the
carry-in signal as cin,
the carry-out as cout,
and the result bit as s.
The
truth table comes directly from the definition of addition and appears
in
Figure 4.11 of P&H.
a b cin s cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Inspecting the
table, we see that s
is 1
if and only if the number of 1’s in the input is odd. We may recognize
this as
the xor of a, b, and cin[1].
The carry-out signal is also an easily recognizable function. It is the
majority function—cout takes on the value of the majority
of its
inputs. As a Boolean function, cout
= a·b + a·cin +
b·cin. This function says that the output cout is 1 if at least
two of its inputs are 1.
For this
exercise, you also need to know how to generate the overflow signal for
an
n-bit 2’s complement adder. There is an
overflow if the carry-out from the most significant adder stage is
different
from the carry-in to that stage.
At this point, you have
everything you
need to know to work out the details of the adder/subtractor circuit.
Remember, the best
circuit designs take advantage of hierarchy, and an adder/subtractor
circuit exhibits a
natural hierarchy.
The
Exercise
Based on
the truth table and boolean expressions presented above, and your
understanding
of multi-bit ripple-adders, design and implement in Verilog a 4-bit
adder/subtractor. Your design should
include three Verilog
modules (all in one file). You will
have a1-bit adder module, a 4-bit adder/subtractor module , and a
test-bench module for
your 4-bit adder/subtractor.
Your design
must include gate delay. Use a
value of 1ns for every gate in your design.
Use the following module and
port names
for your 4-bit adder/subtractor:
module addSub4 (A, B, Op, R, overflow);
input [3:0] A,B;
input Op;
output [3:0] R;
output overflow;
The Op bit in
the input specifies the
operation to be performed and is 0 for add and 1 for subtract.
Your test-bench should
print out
the adder/subtractor input and output values, and the expected output
values. For this exercise, it is simplest
to
display, specify in your test-bench, and print your input and output
values all
in binary instead of decimal. Debug and
verify the correct operation of your adder with at least the following
test
cases:
Compiling
and Simulating Your Design
Verilog
files have the extension “.v”. The command to compile such files is
iverilog -tvvp -Wall -o <output
file>.vvp <input file>.v
Option “–tvvp” indicates that
the output
is a complete program that simulates the design but must be run using
the
command vvp. By
convention, we
name the output file with the extension “.vvp”.
After your modules compiles sucessfully, you can simulate the
design with the following command:
vvp
<file>.vvp
For more information on
iverilog and vvp,
try “man iverilog” and “man vvp”.